1. Technical Field
The present invention relates to integrated circuit testing and more particularly to a device, system and method having a disposable built-in self-test portion which can be removed after testing.
2. Description of the Related Art
Integrated circuits which are built by stacking two or more layers of conventional chips to create three-dimensional (3-D) integrated circuits have several unique problems pertaining to testability. First, given that the functional yield of circuits is generally less than 100%, assembling untested chips can result in a very low yield for the 3-D chip. Second, single layers of a stack may not have completed circuits, as they may be utilizing additional layers for function, load, or wiring, and hence, these single layers may not be testable. For example, a regulator layer may need to be tested; however, the regulator layer needs a load to properly be tested. The load is typically located on another layer.
Third, in order to test each layer, probe pads have to be placed on each tested layer. These probe pads waste silicon area since they are unused after assembly.